Method and apparatus to optimize an integrated circuit design using transistor folding

ABSTRACT

A method and system are disclosed to optimize an integrated circuit layout design by determining possible lengths of layout rows that will reduce the total area of the integrated circuit layout (FIG.  4 B). The possible row lengths ( 401 B) are determined and stored in a memory unit as a set of possible optimal row length values. A set of possible optimal row heights corresponding to the determined set of possible rowlengths is determined and the total chip area is iteratively calculated. Optimal values of rowlength and row height are chosen based upon the maximum chip area reduction. Once the optimal row length and height parameters are chosen, transistor devices placed in each row of the integrated circuit layout are folded to achieve the optimal row length and height.

CROSS-REFERENCE TO RELATED APPLICATIONS

The present application claims priority from International ApplicationNo. PCT/US01/10557, filed on Mar. 30, 2001, which claims the benefit ofU.S. Provisional Application Ser. No. 60/193,601, flled on Mar. 31,2000, both of which are hereby incorporated by reference in theirentireties for all purposes as if fully set forth herein.

1. TECHNICAL FIELD

The invention relates to a system and method of optimizing integratedcircuits (ICs), and in particular to a system and method for providingan optimal IC layout designs using transistor folding.

2. BACKGROUND

As designers strive to improve the capabilities of new ICs, minimizationof IC size continues to be an underlying goal. Typically, IC designsutilize previously developed circuit designs, from a library of circuitdesigns in new combinations and configurations to create wholly newdesigns capable of performing new functions or perhaps optimizing theperformance of the previous IC designs. While some individual IC designshave been optimized in terms of performance and size, the combination ofthese circuits with other circuits into new custom designed ICs oftenutilize a re-configuration of transistor geometry to provide the optimaldesign of the overall new custom designed IC.

When custom designing a new high performance IC, individual transistorsmay be tuned to provide optimal speed. However, manually tuningindividual transistor is both tedious and error-prone. While someautomated transistor sizing tools exist to optimize individualtransistors, the individual transistors still benefit from an optimalphysical layout design to provide an optimal IC. Conventional layoutdesigns place individual transistors on a layout using a row-baseddesign style. In most cases, conventional row-based layout designsresult in an inefficient utilization of chip area because the individualtransistors are of non-uniform size and shape.

Transistor folding is a method of re-configuring the geometry of a knowntransistor design in order to minimize total chip area, while retainingthe performance characteristics of the known design. In custom ICphysical layout design, high performance requirements of new circuitdesigns nay necessitate the integration of various transistor devices ofdifferent sizes. In the typical row-based layout design style,non-uniform transistor heights in a row tend to waste overall IC chiparea. Therefore, it is highly desirable to provide a system and methodof transistor device folding which takes advantage of the differentrows' lengths to achieve efficient area utilization of the entire IClayout.

3. SUMMARY

Accordingly, the present invention seeks to provide an IC design with anoptimal chip area. An embodiment of the present invention is directed toa system and method of chip area optimization using row-based transistorfolding techniques with a global impact analysis. By analyzing eachtransistor device placed in an IC layout, the embodiment may determinehow best to re-configure the geometry of individual transistor, throughthe use of transistor folding, in order to optimize the size of theoverall IC. The chip area that is optimized may consist of both thetransistor area and the routing area. Another embodiment provides forsizing optimization in two dimensions. Moreover, another embodimentfurther analyzes the electrical impact transistor folding will have oneach device placed within the IC layout. The embodiment utilizes thisanalysis to provide adequate routing area between rows to reduceparasitic electrical effects in its optimization process. Still further,another embodiment provides IC sizing optimization in a time that islinearly related to the overall number of transistors integrated withina single device. The transistor folding techniques of the variousdisclosed embodiments in conjunction with transistor sizing are designedto optimize the IC at the layout stage.

4. BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram of a computer system that may be used in connectionwith various embodiments of the invention as described herein;

FIG. 2 is a diagram of a simplified integrated circuit as may berepresented in the form of a virtual component block;

FIG. 3 is a diagram of a general process flow for a circuit design,illustrating various levels of circuit abstraction;

FIGS. 4 a and 4 b illustrate the principle of transistor folding;

FIG. 5 illustrates an example of a physical layout after transistorsizing;

FIG. 6 illustrates an example of the optimized physical layout aftertransistor folding.

5. DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments will now be described, with reference as necessaryto the accompanying drawings.

Systems and methods are disclosed for physical layout of ICs in whichtransistors are folded in a manner to achieve efficient component layoutby taking advantage of differences in the lengths of different rows inthe circuit layout. To provide some useful context, this descriptionwill first discuss a preferred embodiment of a computer system andmethod for designing and creating integrated circuit chips.

By way of general background, chip designers often use electronic designautomation (EDA) software tools to assist in the design process, and toallow simulation of a chip design prior to prototyping or production.Chip design using EDA software tools generally involves an iterativeprocess whereby the chip design is gradually perfected. Typically, thechip designer builds up a circuit by inputting information at a computerworkstation generally having high quality graphics capability so as todisplay portions of the circuit design as needed. A top-down designmethodology is commonly employed using hardware description languages(HDLs), such as Verilog® or VHDL, for example, by which the designercreates an integrated circuit by hierarchically defining functionalcomponents of the circuit, and then decomposing each component intosmaller and smaller components.

Two of the primary types of components used in integrated circuits aredatapaths and control logic. Control logic, typically random logic, isused to control the operations of datapaths. Datapath areas of thecircuit perform functional operations, such as mathematical or otheroperations.

The various components of an integrated circuit are initially defined bytheir functional operations and relevant inputs and outputs. Thedesigner may also provide basic organizational information about theplacement of components in the circuit using floorplanning tools. Duringthese design states, the designer generally structures the circuit usingconsiderable hierarchical information, and has typically providedsubstantial regularity in the design.

From the HDL or other high level description; the actual logic cellimplementation is typically determined by logic synthesis, whichconverts the functional description of the circuit into a specificcircuit implementation. The logic cells are then “placed” (i.e., givenspecific coordinate locations in the circuit layout) and “routed” (i.e.,wired or connected together according to the designer's circuitdefinitions). The placement and routing software routines generallyaccept as their input a flattened netlist that has been generated by thelogic synthesis process. This flattened netlist identifies the specificlogic cell instances from a target standard cell library, and describesthe specific cell-to-cell connectivity. In addition, the method andsystem described herein may be used with a full customized design,wherein the transistor cells are fully customized by the designer.

Further explanation of a particular chip design process, with emphasison placement and routing of datapaths, is set forth, for example, inU.S. Pat. No. 5,838,583, hereby incorporated by reference as if setforth fully herein. Various embodiments as described herein relate inparticular to the task of placing logic cells to arrive at a circuitlayout.

FIG. 1 is a diagram of a computer system that may be used in connectionwith various embodiments of the invention as described herein. As shownin FIG. 1, a computer system 100 includes a computer 110 connected to adisplay 191 and various input-output devices 192. The computer 110 maycomprise one or more processors (not shown), as well as working memory(e.g., RAM) in an amount sufficient to satisfy the speed and processingrequirements of the system. The computer 110 may comprise, for example,a SPARC™ workstation commercially available from Sun Microsystems, Inc.,or any other suitable computer.

The computer 110 contains stored program code including, in oneembodiment, a datapath floorplanner 120, a datapath placer 130 and arouting space estimator 140. The datapath flooplanner 120 provides forthe definition of datapath functions, datapath regions, and constraintson these for the purpose of interactive floorplanning operations by thecircuit designer, and the control of placement operations of thedatapath placer 130. The datapath placer 130 determines the placement ofdatapath functions within datapath regions, and the placement of logiccell instances within each datapath function, according to theconstraints defined by the circuit designer. The routing space estimator140 estimates routing space used for routing the datapath functions,given the placement of such functions by the datapath placer 130.

In support of the above-mentioned system components, a chip floorplanner150, global/detail router 160, standard cell placer 170, logicsynthesizer 180, and HDL editor 190 may be usefully employed. Operationof the chip floorplanner 150, global/detail router 160, standard cellplacer 170, logic synthesizer 180, and HDL editor 190 is conventional,as the design of these components is well known in the art of electronicdesign automation. Commercially available examples of these systemcomponents are Preview™, Cell3™, QPlace™, Synergy™, and Verilog®,respectively.

The computer 110 is preferably coupled to a mass storage device (e.g.,magnetic disk or cartridge storage) providing a layout database 195 withwhich the foregoing system components interface. The layout database 195may be implemented using the EDIF database standard. The computer 110may also comprise or be connected to mass storage containing one or morecomponent libraries (not shown) specifying features of electricalcomponents available for use in circuit designs.

Referring now to FIG. 2, there is shown a schematic illustration of asimplified integrated circuit 200 that may be represented by virtualcircuit design data stored in the layout database 195. In actual, morerealistic integrated circuit designs, the integrated circuit 200 wouldbe far more complicated. However, FIG. 2 is useful for purposes ofillustration. As shown therein, the integrated circuit 200 comprises ofa plurality of control regions 201, datapath regions 203, and memory205. The various control regions 201, datapath regions 203 and memory205 are interconnected with databuses 207 generally spanning multiplebits. Each datapath region 203 may comprise a plurality of datapathfunctions 209. A datapath function 209 may utilize some or all of thebits available from the databus 207. A datapath function 209 maycomprise a plurality of cell instances 215 which enable some form ofsignal or logic transformation of the data passed by the databus 207.The cell instance 215 within a datapath function 209 generally operateson the data carried on the datapath function 209.

As represented in the schema of the layout database 195, the integratedcircuit 200 is comprised of a plurality of instances and a plurality ofnets. A net interconnects a number of instances, by associating pins oneach of the instances.

FIG. 3 is a diagram of a general process flow for a circuit design,illustrating some of the various levels of circuit abstraction asdescribed above. As illustrated in FIG. 3, a register transfer logic(RTL) file 301 in the form of an HDL file or other high level functionaldescription undergoes a compile process 303, which typically includessome form of logic synthesis, and converts the functional description ofthe circuit into a specific circuit implementation which may be storedin the form of a netlist file 304. As part of the compile process 303, acomponent library 306 is generally referenced, which stores informationconcerning what types of design components are available, and thecharacteristics of those design components which are needed in order todetermine their functional connectivity. At this process stage, someattempt may be made at circuit optimization in order to minimize thenumber of components used in the circuit design. The netlist file 304,as previously noted, generally identifies the specific logic cellinstances from a target standard cell library, and describes thespecific cell-to-cell connectivity.

By application of a physical design process 309 shown in FIG. 3, thelogic cells of the netlist file 304 are then placed and routed,resulting in a layout file 310. The component library 306 is utilized inthis process stage in order to obtain information concerning the sizesof gates and other components that may be present in the netlist file304.

From the layout file 310, a verification process 312 may be run, asfurther illustrated in FIG. 3, resulting in a mask file 315 in, forexample, a GDSII or CIF format. The mask file 315 may be provided to afoundry, and contains enough information to allow the foundry tomanufacture an actual integrated circuit therefrom.

According to the preferred embodiments as described herein, the physicaldesign process 309 includes a process to efficiently layout a circuitdesign in part by transistor folding in a manner so as to take advantageof the different row lengths in the integrated circuit 200. Preferably,the netlist file 304 which identifies the specific logic cell instancesfrom a target standard cell library (e.g., component library 316) orfrom the full custom designed transistor cells and which describes thespecific cell-to-cell connectivity, is used as an input to the process.The resulting output from the process is a layout file 310 containing anefficient component layout for the integrated circuit 200, includingfolded transistors.

Transistor folding techniques described herein may be implemented as acomputer program on the computer system 100 described previously forintegrated circuit chip design. In addition, some or all of the methodssteps performed in the present invention may be implemented as hardware(e.g., using a programmable logic device), or a combination of hardwareand software. Additionally, some or all of the method steps may beimplemented using a computer usable/readable medium that is usable by aprocessor to execute the inventive methods. The associated methods maybe partially or completely automated. The resulting layout file 310 fromthe disclosed processes may be used to create an integrated circuit chip200 with components arranged to achieve efficient spatial utilization.

In one embodiment as disclosed herein, for a circuit design havingtransistors laid out in rows, a method for area layout reductionincludes the steps of determining the maximum row length, determining aset of possible row lengths for each row, selecting a row length foreach row resulting in the most area reduction for that row, determininga minimum height after folding for each row, determining a set ofpossible new heights for each row, and selecting a new height for eachrow from the set of possible new heights, the new height being above therow's minimum height but below the row's current height, such that thearea of the layout is reduced. Selection of the new height for each rowmay involve an iterative process wherein each possible new height istested and the resulting savings in area calculated. Once the new heightis selected, transistors in the given row are folded to accommodate thenew height.

FIGS. 4 a and 4 b illustrate a basic physical design process 309 inwhich a transistor device 401 a is folded to achieve a more efficientcomponent layout. FIG. 4 a depicts a transistor device 401 a having aheight W and comprising a source area S, gate area G, and drain area D.In FIG. 4 a, transistor device 401 a is shown to have a minimum spacebetween the contact and diffusion l_(cd), a length of the contact l_(c),and a minimum space between the contact and poly-silicon area l_(cp). Asshown in FIG. 4 a, the transistor device 401 a has been placed underhigh congestion area 402. In the example depicted in FIG. 4 a,transistor device 401 a may represent the tallest transistor deviceplaced in the row. Disposed above transistor 401 a are regions of highcongestion area 402 and low congestion area 403. Areas 402 and 403 mayrepresent additional transistor elements or their respective routinglayers which may cause electrical interference if placed too closely totransistor device 401 a. Areas of high congestion (402) may contain alarge number of transistors or routing elements whereas areas of lowcongestion may contain fewer to no elements, which cause electricalinterference upon transistor 401 a. FIG. 4 a also depicts an area to theright of transistor device 401 a, directly beneath low congestion area403. As this area contains no transistor device cells, preventsefficient utilization of the IC chip area is not achieved.

As the distance between diffusion areas of the transistor device 401 aand the high congestion area 402 decreases, the probability parasiticelectrical effects affecting the performance of the transistor device401 a increases. In addition, it may be the case that as the distancebetween diffusion areas of the transistor device 401 a and the highcongestion area 402 decreases, completion of the IC design is notpossible. This is because the routing between rows on a layout may notbe placed in the limited space between diffusion area and congestionarea. A minimum distance K must be reserved between rows to allow forrouting between rows. By increasing the minimum distance between rowsthe probability of performance degradation of transistor device 401 adecreases. Alternatively, a transistor device may be folded to decreasethe height requirement and the entire total chip area of the IC isdecreased. Thus, the reserved distance K between rows is maintained andthe total chip area is decreased.

FIG. 4 b illustrates the same transistor device 401 b after it hasundergone a re-configuration of its geometry. As shown in FIG. 4 b,transistor device 401 b retains the same l_(cd), l_(c), l_(cp)dimensions so that no additional parasitic effects occur as a result ofthe folding technique. Additionally the electrical contacts andperformance of transistor device 401 b provide the same results astransistor 401 a. However, as shown in FIG. 4 b, the distance betweenthe diffusion area of transistor device 401 b to the high congestionarea 402 increases by ⅔ W. Thus, the performance of the circuit may bedramatically improved and less likely to be subject to parasiticeffects. As a result, both areas 402 and 403 may subsequently be loweredon the actual physical layout of the IC without degrading theperformance of the IC. Thus, the total chip area of the IC may be moreefficiently utilized.

Next, the impact transistor folding has on the transistor performance isdiscussed. Referring again to FIGS. 4 a and 4 b, the main concern withtransistor folding is whether the performance of the transistor deviceafter folding is better, worse than or the same as the performancebefore the folding. The main factors that affect the performance of thetransistor in the layout view are the parasitic parameters, such AS(area of source), AD (area of drain), PS (periphery of source), and PD(periphery of drain). These parasitic parameters will affect theparasitic computation of the transistor and result in the differentdelays of the transistor. Because of the symmetry of the source anddrain, the analysis of AD and PD are the same as AS and PS. Thus, onlyan analysis of AS and PS is performed. Before the folding, AS can becalculated as:AS _(before) =W(l _(cd) +l _(c) +l _(cp))  (1)where W is the width of the transistor. The value of l_(cd) is theminimum space between the contact and the diffusion. l_(c) is the lengthof the contact and l_(cp) is the minimum space between the contact andthe poly region. After the folding, the source S has been split as twosources connected by a local wire, as shown in FIG. 4 b. The new AS canbe calculated as:AS _(after)=⅓W(l _(cd) +l _(c) +l _(cp))+⅓W(l _(cp) +l _(c) +l_(cp))  (2)Comparing AS_(after) with AS_(before):AS _(before) −AS _(after)=⅓W(2l _(cd) +l _(c))  (3)In an embodiment, the value of AS_(before)−AS_(after) is always greaterthan 0, which means the parasitic AS is reduced after folding. Thesmaller AS improves the transistor performance in terms of speed.

Next, the PS analysis is performed. Before the folding PS_(before) is:PS _(before)=2(W+l _(cd) +i _(c) +l _(cp))  (4)After folding, PS_(after) is:PS _(after)=2(⅓W+l _(cd) +l _(c) +l _(cp)+⅓W+l _(cp) +l _(c) +l_(cp))  (5)Comparing PS_(after) with PS_(before):PS _(before) −PS _(after)=2(⅓W+l _(cd) −l _(cp))  (6)The value of PS_(before)−PS_(after) is greater than 0 in many cases.Therefore, in many cases, folding the transistor also reduces theparasitic parameter PS.

Transistor folding further improves the IC performance by benefiting therouting between the various transistor devices incorporated into theoverall IC. When a transistor device is folded, two regions on the IClayout will be affected. In FIGS. 4 a and 4 b, areas 402 and 403 areshown as the two areas affected by transistor device folding. Areas 402and 403 may contain either an area of high congestion or low congestion.While in FIGS. 4 a and 4 b, area 402 is depicted as high congestion areaand area 403 is depicted as low congestion area, statistically there arefour combinations of areas 402 and 403 that may occur. The benefits oftransistor folding may affect the overall performance in a variety ofways depending upon the configuration of the surrounding transistordevices.

Case 1: Area 402 is a high congestion area for routing, area 403 is aless congested area. After folding, there will be approximately ⅔W extraspace for the routing. The wires for connecting the source and drain caneither use that space to connect the first source and drain terminals onthe left side or use area 403 to connect the first source and drainterminals on the right side. Either way can reduce the burden of thehigh congestion area 402.

Case 2: Area 402 is a high congestion area, area 403 is also a highcongestion area. After transistor folding, these congestion areas willbe alleviated by using the extra space ⅔W provided to them for routingafter the transistor folding.

Case 3: Area 402 is a less congested area, area 403 is also a lesscongested area. The transistor folding impact on the routing may not besignificant, since ample area for routing is provided between thetransistor device and areas 402 and 403 both before and after transistorfolding.

Case 4: Area 402 is a less congested area, area 403 is a high congestionarea. Since adequate space is available for routing wires before thetransistor folding, the connecting wires for the source and drain can gofrom the area 402. Thus, in this case, the transistor folding impact onthe routing may not be significant.

Overall, from the above four cases, it can be seen that transistorfolding can benefit routing. In many cases, it alleviates overcrowdingof certain areas upon the IC layout. Thus, transistor folding continuesto improve the performance of each individual transistor device.

While it has been shown above that several electrical characteristics ofthe resulting folded transistor device are improved, the introduction ofadditional wires to connect the folded source and drain terminals mayslightly degrade the performance of the transistor device 401 b.Referring to FIGS. 4 a and 4 b, the resulting source and drain terminalsof folded transistor 401 b are separated from one another after thefolding procedure and may require an additional length of wire tore-connect the terminals. The additional length of wire is introduced tothe connecting wire for S is approximately 2l_(c)+4l_(cp)+2l_(p) (thedistance between the two source terminals in folded transistor 401 b).l_(p) is the poly wire width. Before folding, the local wire length forthe source terminals S is W. After folding, the local wire length for SisS=⅓W+2l _(c)+4l _(cp)+2l _(p)  (7)

Therefore, whether the wire becomes longer or shorter is determined bythe difference between ⅔W and 2l_(c)+4l_(cp)+2l_(p). If ⅔W is greaterthan 21_(c)+41_(cp)+21_(p), then the wire becomes shorter after thefolding and the performance of the transistor will be better. Otherwise,the wire becomes longer and the performance of the translator may bedeteriorated. Despite the potential for a slight degradation in ICperformance due to an increased length of local wire connecting thevarious folded source and drain terminals, it can be seen thattransistor folding not only re-configures the geometry of a transistordevice, but may also help to improve transistor performance.

The preferred method described herein seeks to utilize transistorfolding at the layout stage to achieve the minimum chip area for anentire IC. A chip area consists of both area occupied by the transistordevices and the area occupied by the necessary routing area.

Due to design constraints the area occupied by transistor devices withinan IC will utilize a minimal required area. Thus, in one embodiment thecalculation of transistor area is:Area_(transistors)=Σrowheight_(i)*maxrowlength  (8)rowheight_(i)=maxW _(ji) subject to W _(ji)≧MINSIZE  (9)where rowheight_(i) is the height of the ith row. W_(ji) is the width ofthe jth transistor in row i. Maxrowlength is the longest row's length ofthe layout. It includes the diffusion gap and space between thetransistors in the same row for routing. MINSIZE is the minimumtransistor size. For simplicity, MINSIZE is used instead of usingPMINSIZE and NMINSIZE separately. PMINSIZE represents the minimum sizeof pfet transistors and NMINMIZE represents the minimum size of nfettransistors.

Optimization of the actual physical layout of the IC can additionallyinvolve minimizing the area occupied by the routing. By reducing therouting area, the total chip area of the IC may be reduced. In thedesigning of the layout that will undergo transistor folding, a verticalspace K is already reserved for the routing between rows. However, thefolding procedures for the transistors change the shapes of thetransistors and may further affect the routing. The estimation of therouting area changed due to the transistor fold is difficult if thetransistor folding procedure is executed before the layout. However, inthe various embodiments, the estimation is facilitated, because avertical space K has already been reserved for the routing and anychanges for the existing wire due to the transistor folding can beassumed as the local changes. Thus, in this embodiment the calculationof the routing area for each row is:Area_(routing)=(K+S _(ji)(n))*maxrowlength  (10)where K is defined above as the space reserved for the routing betweenrows. S_(ji)(n) is the additional space introduced locally by thetransistor j at row i with ii folds due to folding.

The following will describe the manner in which S_(ji)(n) is calculatedin an embodiment of the invention. In the example illustrated in FIGS. 4a and 4 b, the transistor device 401 a represents a transistor devicethat is incorporated in a new custom IC design before folding.Transistor device 401 b depicts transistor device 401 a folded into 3transistors. It can be seen that only two local wires (two tracks) areneeded for connecting the same source (S) terminals and drain (D)terminals. For other folding numbers, such as 5,7,9 . . . folds, onlytwo local wires are needed for connecting the same source/drainterminals. Therefore, a method of an embodiment sets the routingoverhead S_(ji)(n) as a constant. Setting Q=K+S_(ji)(n), Q is then alsoset as a constant.

By adding up the transistor area and routing area. The objectivefunction becomes:minimize(Σrowheigt_(i) +Q)*maxrowlength)  (11)Thus, the present method determines how to fold each transistor toreduce the area of physical layout by taking the advantage of differentrows' lengths.

From Equation 11, the total chip area of the IC may be reduced byreducing the heights of the rows and finding the optimal maxrowlengthwhich can give freedom for each row to fold the transistors in the rowto achieve the maximum area reduction.

According to Equation 11, the area is determined by two items,maxrowlength and Σrowheight_(i). Therefore, the system and method of theembodiment optimizes the overall chip area in two-phases. Phase Idetermines the maxrowlength. Phase II determines row height. By doingthis, the method and systems solves the two-dimensional transistorfolding problem.

Phase I: Finding Maxrowlength In this phase, the maxrowlength iscalculated. From the layout after transistor sizing, the initialmaxrowlength_(init) is identified Each row can become the longest rowafter folding the transistors in that row. The length of row j can berepresented as:rowlength_(j) =a ₁ l ₁ +a ₂ l ₂ + . . . +a _(i) l _(i) + . . . a _(n) l_(n)  (12)Where l_(i) is the length of transistor i in the row and includescontacts etc. a₁, a₂ . . . , a_(n) are integers. a_(i) indicates howmany splits transistor i has. The range of a_(i) can be represented by:$\begin{matrix}{1 \leq a_{i} < \frac{{LENGTHLIMIT} - {{initial}\quad{{row}'}s\quad{length}}}{l_{i}}} & (13)\end{matrix}$where LENGTHLIMIT is the limit of the row length, which is user defined.The number of all possible lengths of row j is: $\begin{matrix}{\prod\limits_{i = 1}^{m}\quad\left( \frac{{LENGTHLIMIT} - {{initial}\quad{{row}'}s\quad{length}}}{l_{i}} \right)} & (14)\end{matrix}$where m is the numbers of transistor in row j. Among all possiblelengths, the bestrowlength_(j) for row j can be found to achieve thebest area reduction due to the folding. Bestrowlength_(j) can be longerthan maxrowlength_(initial) as long as:bestrowlength_(j)×(H−ΔH)≦max rowlength_(init) ×H  (15)where H is the height of row j. ΔH is the amount of the height of therow that will be decreased due to the folding.

After Phase I, the method builds a set (S) of bestrowlength_(j) bychoosing the bestrowlength_(j) which is greater thanmaxrowlength_(init). Each value in the set (S) is a potentialmaxrowlength. Because it may not known which one results in the maximumtotal area reduction of the layout, each will be used in Phase II tofind the maximum area reduction.

Phase II: Folding Transistors

In this phase, the area reduction for folding transistors based on eachmaxrowlength is calculated and the maximum area reduction as the finalresult is selected. In order to reduce the computation, minh is firstcalculated for each row. minh is the possible minimum height of the rowafter folding. The transistor device heights that are greater than minhare possible solutions. The following equation calculates the minh.$\begin{matrix}{{\sum{\left( \frac{h_{i}}{\min\quad h} \right) \times l_{i}}} \leq {\max\quad{rowlength}}} & (16)\end{matrix}$

Because one goal is to minimize minh, the above equation becomesΣ(h_(i)/minh)*l_(i)=maxrowlength The idea of introducing minh can beused to reduce the computation.

Referring to FIGS. 5 and 6, the method is described by way of anexample. FIG. 5 illustrates a sample IC layout. Known transistor devices501, 502, 503, and 504 are placed onto the IC substrate 500 in row 1.Transistor device 505 is placed onto the IC substrate in row 2. Thelengths of transistor devices 501, 502, 503, 504, and 505 are 4, 4, 6,4, and 40, respectively. The heights are 12, 4, 8, 15, and 4,respectively. Suppose transistor device 505 is a macro cell whosegeometry cannot be modified. In Phase I, the method finds the initialmaxrowlength is 40 (the length of transistor device 505 in row 2). Forrow 2, the method finds the possible maxrowlength, it is still 40. InPhase II, the method first calculates the minh of row 1:((12/minh)*4)+((4/minh)*4)+((8/minh)*6)+((15/minh)*4)=40  (17)Solving for minh, the equation yields minh=4.3. Keeping in mind that theminimum height possible is 4.3, the method then calculates the possibleheights of each transistor in the row as it is folded. Transistor device501, for example, begins with an initial height of 12. Foldingtransistor 501 into 2 segments yields a new height of 6. Foldingtransistor 501 into 3 segments yields a height of 4. This is not apossible solution for the height of row 1 as it does not meet the minhof 4.3. Referring to transistor 502, the initial height of thetransistor is already denoted to be 4, thus no further folding oftransistor 502 is needed. Transistor 503 is initially designed with aheight of 8. Folding transistor 503 into 2 segments yields a transistorheight of 4. Transistor 504 is designed with an initial height of 15.Folding this transistor into 2 segments yields a transistor with aheight of 7.5 (rounded to be 8). Folding transistor 504 into 3 segmentsyields a transistor with a height of 5. Any further folding oftransistor 504 will not yield a possible height solution as it will belower than the calculated minh. Thus, the possible height solutions forrow 1 are 8, 6, or 5.

A transistor may be folded an integral number of times. Solving for thelength of row 1 for a height of 8, the length is found to beapproximately 26. Solving for a height of 6, the length is approximatedto be 36. Setting the height of row 1 to 5 provides a row length of 40.If the height of row 1 is set any lower than 5, the length of row 1exceeds the maxrowlength of 40. At this point each transistor is foldedsuch that their heights do not exceed the row height of 5.

FIG. 6 illustrates the final optimized physical layout of the IC. Byfolding the transistor 501, 502, 503, and 504 additional space isallotted between rows. This space can be used either to incorporateadditional transistor devices within the IC substrate or may provideadditional spacing to counteract any potential parasitic effect.

The method described herein may be performed by the computer systemdescribed earlier in FIG. 1. The computer 110 contains a stored programcode to implement the steps of the optimization method. The possiblestored code for Phase I may be as follows:

for each row for(each transistor in the row) { find.possible.fold.size(w₁, w₂, . . . w_(n)) } for(each set of possible height) { merge( ),merging all possible transistor heights. } for(each possible transistorheight) { find the bestrowlength _(j) }

In line 3 of the above code, w_(n)=h_(i)/n; where w_(n)≧MINSIZE, andh_(i) is the height of transistor i. Since any transistor can be foldedonly by multiple-integrals, the possible heights of transistor i arerepresented by the equation h_(i)/n, where (h_(i)/n≧MINSIZE). Lines 2-4,of the exemplary code, calculate all the possible heights of eachtransistor in the row. Next, lines 5-7 merge all calculated possibleheights of the transistors into a set of monotonously decreasingpossible row heights. Finally, lines 8-9 compute area reduction and findthe maximum area reduction. The bestrowlength_(j) is also calculatedfrom lines 8-9.

The possible stored code for Phase II may be as follows:

for each maxrowlength for each row find the minimum row's height (minh)based on the current maxrowlength (maxrowlength). for each height fromthe highest possible height to minimum row's height estimate the foldingeffect, if (new rowlength < maxrowlength) continue; if (new rowlength ≧maxrowlength) find the new row's length and break; end end end find themaximum area reduction. folding transistors.

Note that in the loop of the above procedure, the transistors for eachpossible maxrowlength are not actually folded. Rather the originaltransistor geometry information is kept so that the estimation of thearea reduction for the next possible maxrowlength may be calculated.Once the maximum are reduction is calculated the HDL editor 190 mayre-configure the geometry of each transistor device through the use of afolding technique.

The complexity of lines 2-4 of the exemplary stored code for Phase I maybe represented by the function O(n), where n is the number of thetransistors in the circuit. Thus, the amount of time to process andperform the function denoted by lines 2-4 of the stored code is directlya function of the number of transistor in the circuit. Furthermore, thecomplexity of lines 5 and 6 are also represented by the same functionO(n). In line 3 of the stored code, a set of sorted possible heights isgenerated for each transistor. The time needed to generate the set is alinear function of the transistors in the set. Likewise, the complexityof lines 8-9 is also represented by the function O(n). Thus, the timeneeded to calculate the maxrowlength is linearly related to the numberof transistors in the circuit.

In Phase II, the number of maxrowlength may be represented as Q, and thenumber of rows may be represented by m. Thus, the total number ofpossible heights of each row is p*n/Q, where p is the maximum number ofpossible heights of each transistor. Therefore, the total complexitywill be O(Q*m*p*n/Q). Simplifying the function, the resulting complexityfunction is represented as O(m*p*n). In the usual case, m and p arebounded. Therefore, the complexity of Phase II of the method can berepresented by the function O(n). In the worst case, m=n, the complexityof the algorithm takes on the form of O(n²). As the situation where eachrow has only one transistor (i.e., m=n). On average, the computationcomplexity of the method is O(n). Thus, the method described herein canbe said to have a computational complexity of O(n). Therefore, the timeneeded to complete the optimization method described herein is linearlyrelated to the total number of transistors in the circuit.

A system and method of practical transistor folding has been describedherein which can be used in the high performance IC physical designflow. The system and method takes the advantage of different rows'lengths and introduces the possible minimum row's height (minh) whichreduces the computation. The experimental results show the efficacy ofthe algorithm.

While preferred embodiments of the invention have been described herein,many variations are possible which remain within the concept and scopeof the invention. Such variations would become clear to one skilled inthe art upon perusal of the description of the embodiments set forthherein.

1. A method of optimizing an integrated circuit layout comprising thesteps of: a) calculating a first total chip area of a first proposedlayout, the first proposed layout representing transistor devices placedon the integrated circuit layout; b) determining a possible rowlengthvalue that produces a modified total chip area less than the first totalchip area; c) calculating a minimum row height corresponding to thedetermined possible rowlength value; d) iteratively varying the heightvalue of a row, wherein the height is greater than the minimum rowheight; e) calculating a value of the modified total chip area using thedetermined possible rowlength value and iteratively varied height value;f) iteratively repeating steps b) through e) to determine an optimaltotal chip area; and g) generating an optimal integrated circuit layout.2. The method of claim 1, wherein the step of calculating a minimum rowheight comprises dividing the sum of areas of transistor devices placedin the first proposed layout by the determined possible rowlength. 3.The method of claim 1, wherein the step of calculating a first totalchip area comprises multiplying a maximum rowlength of the firstproposed layout by a first total height of the first proposed layout. 4.The method of claim 1, wherein the step of calculating a modified totalchip area comprises calculating a total rowheight value by adding aconstant Q to the iteratively varied height value, wherein the constantQ represents a sum of a reserved space for routing between rows and anadditional space that is introduced locally to each transistor as aresult of transistor folding; calculating a second total height byadding the total rowheight of each row; and multiplying the second totalheight by the determined possible rowlength value.
 5. The method ofclaim 1, further comprising the step of folding each transistor deviceto achieve the varied height value used for each row of the optimalintegrated circuit layout.
 6. A system for optimizing an integratedcircuit layout comprising: a) means for calculating a first total chiparea of a first proposed layout, the first proposed layout representingtransistor devices placed on the integrated circuit layout; b) means fordetermining a possible rowlength value that produces a modified totalchip area less than the first total chip area; c) means for calculatinga minimum row height corresponding to the determined possible rowlengthvalue; d) means for iteratively varying the height value of a row,wherein the height is greater than the minimum row height; e) means forcalculating a value of the modified total chip area using the determinedpossible rowlength value and iteratively varied height value; l) meansfor iteratively repeating steps b) through e) to determine an optimaltotal chip area; and g) means for generating an optimal integratedcircuit layout.
 7. The system of claim 6, wherein the means forcalculating a minimum row height comprises a means for dividing the sumof areas of transistor devices placed in the first proposed layout bythe determined possible rowlength.
 8. The system of claim 6, wherein themeans for calculating a first total chip area comprises a means formultiplying a maximum rowlength of the first proposed layout by a firsttotal height of the first proposed layout.
 9. The system of claim 6,wherein the means for calculating a modified total chip area comprises:means for calculating a total rowheight value by adding a constant Q tothe iteratively varied height value, wherein the constant Q represents asum of a reserved space for routing between rows and an additional spacethat is introduced locally to each transistor as a result of transistorfolding; means for calculating a second total height by adding the totalrowheight of each row; and means for multiplying the second total heightby the determined possible rowlength value.
 10. The system of claim 6,further comprising a means for folding each transistor device to achievethe varied height value used for each row of the optimal integratedcircuit layout.
 11. A system for optimizing an integrated circuit layoutcomprising: a layout database, wherein the layout database stores knownlayouts for integrated circuit functions; a computer processor forcalculating a first total chip area, a modified total chip area, and aminimum height of a row corresponding to a determined possiblerowlength, the computer processor is further capable of determining thepossible rowlength such that the modified total chip area is less thanthe first total chip area; a row height generator capable of generatingiteratively variable row heights greater than the calculated minimum rowheight; and a display capable of generating an image of the optimalintegrated circuit layout.
 12. A method for area layout reductioncomprising the steps of: placing transistor devices in rows of a firstlayout design, calculating an area value for the first layout design;determining a maximum row length of the first layout design; determininga set of possible row lengths for each row of the first layout design;selecting a row length for each row resulting in a maximum areareduction for that row; determining a minimum height after folding foreach row to achieve the selected rowlength; determining a set ofpossible new heights for each row; iteratively selecting a new heightfor each row from the set of possible new heights, the new height beingabove the row's minimum height but below the row's current height, suchthat the area of the first layout design is reduced; and folding thetransistor devices in each row to conform with the selected new height.13. The method of claim 12, wherein the step of determining the minimumrow height comprises dividing the sum of areas of transistor devicesplaced in the first proposed layout by the determined possiblerowlength.
 14. The method of claim 12, wherein the step of calculatingthe area value comprises multiplying a maximum rowlength of the firstlayout design by a first total height of the first layout design.
 15. Asystem for optimizing an integrated circuit layout comprising: a meansfor placing transistor devices in rows of a first layout design, a meansfor calculating an area value for the first layout design; a means fordetermining a maximum row length of the first layout design; a means fordetermining a set of possible row lengths for each row of the firstlayout design; a means for selecting a row length for each row resultingin a maximum area reduction for that row; a means for determining aminimum height after folding for each row to achieve the selectedrowlength; a means for determining a set of possible new heights foreach row; a means for iteratively selecting a new height for each rowfrom the set of possible new heights, the new height being above therow's minimum height but below the row's current height, such that thearea of the first layout design is reduced; and a means for folding thetransistor devices in each row to conform with the selected new height.16. The system of claim 15, wherein the means for determining theminimum row height comprises means for dividing the sum of areas oftransistor devices placed in the first proposed layout by the determinedpossible rowlength.
 17. A method of designing an integrated circuitlayout comprising: placing a plurality of cells on a first designlayout; folding two or more of the plurality of cells of the firstdesign layout; and determining an optimal height and length parameterfor rows of the first design layout, wherein determining the optimallength parameter comprises: proposing a possible row length value foreach row of the first design layout such that a total chip area isreduced; and storing said possible row length values as a first set inmemory.
 18. The method of claim 17, further comprising calculating aminimum height of each row corresponding to each possible row lengthvalue stored in the set, generating a second set of possible row heightvalues wherein each possible row height is greater than the calculatedminimum height, and storing the second set in memory.
 19. The method ofclaim 18, further comprising iteratively calculating total chip areavalues using each possible row length value stored in the first set andeach possible row height value stored in the second set.
 20. The methodof claim 19, further comprising the step of determining the optimaltotal chip area from the iteratively calculated total chip area values.21. A system for designing an integrated circuit layout comprising:means for placing transistor devices on a first design layout; means forfolding transistor devices in a plurality of cells of the first designlayout; and means for determining an optimal height and length parameterfor rows of the first design layout, wherein the means for determiningthe optimal length parameter comprises: means for proposing a possiblerow length values for each row of the first design layout such that atotal chip area is reduced; and means for storing said possible rowlength values as a first set in memory.
 22. The system of claim 21,further comprising means for calculating a minimum height of each rowcorresponding to each possible row length value stored in the set, meansfor generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, meansfor and storing the second set in memory.
 23. The system of claim 22,further comprising means for iteratively calculating total chip areavalues using each possible row length value stored in the first set andeach possible row height value stored in the second set.
 24. The systemof claim 23, further comprising means for determining the optimal totalchip area from the iteratively calculated total chip area values.
 25. Amethod of designing an integrated circuit layout comprising the stepsof: placing transistor devices on a first design layout; foldingtransistor devices in each row of the first design layout to provide anoptimal total chip area for the integrated circuit layout based on aglobal analysis of the total chip area reduction; and determining anoptimal height and length parameter for rows of the first design layout,wherein determining the optimal length parameter comprises: proposing apossible row length values for each row of the first design layout suchthat a total clip area is reduced; and storing said possible row lengthvalues as a first set in memory.
 26. The method of claim 25, furthercomprising calculating a minimum height of each row corresponding toeach possible row length value stored in the set, generating a secondset of possible row height values wherein each possible row height isgreater than the calculated minimum height, and storing the second setin memory.
 27. The method of claim 26, further comprising iterativelycalculating total chip area values using each possible row length valuestored in the first set and each possible row height value stored in thesecond set.
 28. The method of claim 27, further comprising the step ofdetermining the optimal total chip area from the iteratively calculatedtotal chip area values.
 29. A method of designing an integrated circuitlayout comprising the steps of: placing a number of transistor deviceson a first design layout; determining optimal height and lengthparameters for each row of the first layout design wherein step ofdetermining the optimal height and length parameters in each row occursin a time that is linearly related to the number of transistor devicesplaced on the first design layout and the step of determining theoptimal length parameter comprises proposing a possible row lengthvalues for each row of the first design layout such that a total chiparea is reduced and storing said possible row length values as a firstset in memory; and folding transistor devices in each row of the firstdesign layout to conform with the optimal height and length parameters.30. The method of claim 29, further comprising calculating a minimumheight of each row corresponding to each possible row length valuestored in the set, generating a second set of possible row height valueswherein each possible row height is greater than the calculated minimumheight, and storing the second set in memory.
 31. The method of claim30, further comprising iteratively calculating total chip area valuesusing each possible row length value stored in the first set and eachpossible row height value stored in the second set.
 32. The method ofclaim 31, further comprising the step of determining the optimal totalchip area from the iteratively calculated total chip area values.
 33. Asystem for designing an integrated circuit layout comprising: means forplacing and routing transistor devices on a first design layout; meansfor folding transistor devices of the first design layout based onanalysis of both transistor area and routing area; and means fordetermining an optimal height and length parameter for rows of the firstdesign layout, wherein the means for determining the optimal lengthparameter comprises: means for proposing a possible row length valuesfor each row of the first design layout such that the total chip are isreduced; and means for storing said possible row length values as afirst set in memory.
 34. The system of claim 33, further comprisingmeans for calculating a minimum height of each row corresponding to eachpossible row length value stored in the set, generating a second set ofpossible row height values wherein each possible row height is greaterthan the calculated minimum height, and storing the second set inmemory.
 35. The system of claim 34, further means for comprisingiteratively calculating total chip area values using each possible rowlength value stored in the first set and each possible row height valuestored in the second set.
 36. The system of claim 35, further comprisingdetermining the optimal total chip area from the iteratively calculatedtotal chip area values.
 37. A method for designing an integrated circuitlayout comprising the steps of: placing and routing transistor deviceson a first design layout; folding transistor devices of the first designlayout based on analysis of both transistor area and routing area; anddetermining an optimal height and length parameter for rows of the firstdesign layout, wherein determining the optimal length parametercomprises: proposing a possible row length values for each row of thefirst design layout such that the total chip are is reduced; and storingsaid possible row length values as a first set in memory.
 38. The methodof claim 37, further comprising calculating a minimum height of each rowcorresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory.
 39. The method of claim 38, furthercomprising iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set.
 40. The method of claim 39,further comprising the step of determining the optimal total chip areafrom the iteratively calculated total chip area values.
 41. A computerprogram product embodied on computer readable medium, the computerreadable medium having stored thereon a sequence of instructions which,when executed by a processor, causes the processor to execute a methodfor optimizing an integrated circuit layout, the method comprising: a)calculating a first total chip area of a first proposed layout, thefirst proposed layout representing transistor devices placed on theintegrated circuit layout; b) determining a possible rowlength valuethat produces a modified total chip area less than the first total chiparea; c) calculating a minimum row height corresponding to thedetermined possible rowlength value; d) iteratively varying the heightvalue of a row, wherein the height is greater than the minimum rowheight; e) calculating a value of the modified total chip area using thedetermined possible rowlength value and iteratively varied height value;f) iteratively repeating steps b) through e) to determine an optimaltotal chip area; and g) generating an optimal integrated circuit layout.42. The computer program product of claim 41, wherein the step ofcalculating a minimum row height comprises dividing the sum of areas oftransistor devices placed in the first proposed layout by the determinedpossible rowlength.
 43. The computer program product of claim 41,wherein the step of calculating a first total chip area comprisesmultiplying a maximum rowlength of the first proposed layout by a firsttotal height of the first proposed layout.
 44. The computer programproduct of claim 41, wherein the step of calculating a modified totalchip area comprises calculating a total rowheight value by adding aconstant Q to the iteratively varied height value, wherein the constantQ represents a sum of a reserved space for routing between rows and anadditional space that is introduced locally to each transistor as aresult of transistor folding; calculating a second total height byadding the total rowheight of each row; and multiplying the second totalheight by the determined possible rowlength value.
 45. The computerprogram product of claim 41, further comprising the step of folding eachtransistor device to achieve the varied height value used for each rowof the optimal integrated circuit layout.
 46. A computer program productembodied on computer readable medium, the computer readable mediumhaving stored thereon a sequence of instructions which, when executed bya processor, causes the processor to execute a method for area layoutreduction, the method comprising: placing transistor devices in rows ofa first layout design, calculating an area value for the first layoutdesign; determining a maximum row length of the first layout design;determining a set of possible row lengths for each row of the firstlayout design; selecting a row length for each row resulting in amaximum area reduction for that row; determining a minimum height afterfolding for each row to achieve the selected rowlength; determining aset of possible new heights for each row; iteratively selecting a newheight for each row from the set of possible new heights, the new heightbeing above the row's minimum height but below the row's current height,such that the area of the first layout design is reduced; and foldingthe transistor devices in each row to conform with the selected newheight.
 47. The computer program product of claim 46, whereindetermining the minimum row height comprises dividing the sum of areasof transistor devices placed in the first proposed layout by thedetermined possible rowlength.
 48. A system of designing an integratedcircuit layout comprising: means for placing a number of transistordevices on a first design layout; means for determining optimal heightand length parameters for each row of the first layout design whereinthe means for determining the optimal height and length parameters ineach row occurs in a time that is linearly related to the number oftransistor devices placed on the first design layout and the means fordetermining the optimal length parameter comprises means for proposing apossible row length value for each row of the first design layout suchthat a total chip area is reduced and storing said possible row lengthvalues as a first set in memory; and means for folding transistordevices in each row of the first design layout to conform with theoptimal height and length parameters.
 49. The system of claim 48,further comprising: means for calculating a minimum height of each rowcorresponding to each possible row length value stored in the set; andmeans for generating a second set of possible row height values whereineach possible row height is greater than the calculated minimum height,and storing the second set in memory.
 50. A system for designing anintegrated circuit layout comprising: means for placing a plurality ofcells on a first design layout; means for folding two or more of theplurality of cells of the first design layout; and means for determiningan optimal height and length parameter for rows of the first designlayout, wherein determining the optimal length parameter comprises:means for proposing a possible row length value for each row of thefirst design layout such that a total chip area is reduced; and meansfor storing said possible row length values as a first set in memory.51. The system of claim 50, further comprising: means for calculating aminimum height of each row corresponding to each possible row lengthvalue stored in the set, generating a second set of possible row heightvalues wherein each possible row height is greater than the calculatedminimum height, and storing the second set in memory; means foriteratively calculating total chip area values using each possible rowlength value stored in the first set and each possible row height valuestored in the second set; and means for determining the optimal totalchip area from the iteratively calculated total chip area values.
 52. Acomputer program product embodied on computer readable medium, thecomputer readable medium having stored thereon a sequence ofinstructions which, when executed by a processor, causes the processorto execute a method for designing an integrated circuit layout, themethod comprising: placing a plurality of cells on a first designlayout; folding two or more of the plurality of cells of the firstdesign layout; and determining an optimal height and length parameterfor rows of the first design layout, wherein determining the optimallength parameter comprises: proposing a possible row length value foreach row of the first design layout such that a total chip area isreduced; and storing said possible row length values as a first set inmemory.
 53. The computer program product of claim 52, furthercomprising: calculating a minimum height of each row corresponding toeach possible row length value stored in the set, generating a secondset of possible row height values wherein each possible row height isgreater than the calculated minimum height, and storing the second setin memory; iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set; and determining the optimal totalchip area from the iteratively calculated total chip area values.
 54. Acomputer program product embodied on computer readable medium, thecomputer readable medium having stored thereon a sequence ofinstructions which, when executed by a processor, causes the processorto execute a method for designing an integrated circuit layout, themethod comprising: placing transistor devices on a first design layout;folding transistor devices in a plurality of cells of the first designlayout; and determining an optimal height and length parameter for rowsof the first design layout, wherein the means for determining theoptimal length parameter comprises: proposing a possible row lengthvalues for each row of the first design layout such that a total chiparea is reduced; and storing said possible row length values as a firstset in memory.
 55. The computer program product of claim 54, furthercomprising: calculating a minimum height of each row corresponding toeach possible row length value stored in the set, generating a secondset of possible row height values wherein each possible row height isgreater than the calculated minimum height, and storing the second setin memory; iteratively calculating total chip area values using eachpossible row length value stored in the first set and each possible rowheight value stored in the second set; and determining the optimal totalchip area from the iteratively calculated total chip area values.
 56. Amethod for designing an integrated circuit layout comprising: placingtransistor devices on a first design layout; folding transistor devicesin a plurality of cells of the first design layout; and determining anoptimal height and length parameter for rows of the first design layout,wherein the means for determining the optimal length parametercomprises: proposing a possible row length values for each row of thefirst design layout such that a total chip area is reduced; and storingsaid possible row length values as a first set in memory.
 57. The methodof claim 56, further comprising: calculating a minimum height of eachrow corresponding to each possible row length value stored in the set,generating a second set of possible row height values wherein eachpossible row height is greater than the calculated minimum height, andstoring the second set in memory; iteratively calculating total chiparea values using each possible row length value stored in the first setand each possible row height value stored in the second set; anddetermining the optimal total chip area from the iteratively calculatedtotal chip area values.
 58. A system of designing an integrated circuitlayout comprising: means for placing transistor devices on a firstdesign layout; means for folding transistor devices in each row of thefirst design layout to provide an optimal total chip area for theintegrated circuit layout based on a global analysis of the total chiparea reduction; and means for determining an optimal height and lengthparameter for rows of the first design layout, wherein the means fordetermining the optimal length parameter comprises: means for proposinga possible row length values for each row of the first design layoutsuch that a total clip area is reduced; and means for storing saidpossible row length values as a first set in memory.
 59. The system ofclaim 58, further comprising: means for calculating a minimum height ofeach row corresponding to each possible row length value stored in theset; means for generating a second set of possible row height valueswherein each possible row height is greater than the calculated minimumheight; means for storing the second set in memory; means foriteratively calculating total chip area values using each possible rowlength value stored in the first set and each possible row height valuestored in the second set; and means for determining the optimal totalchip area from the iteratively calculated total chip area values.
 60. Acomputer program product embodied on computer readable medium, thecomputer readable medium having stored thereon a sequence ofinstructions which, when executed by a processor, causes the processorto execute a method for designing an integrated circuit layout, themethod comprising: placing transistor devices on a first design layout;folding transistor devices in each row of the first design layout toprovide an optimal total chip area for the integrated circuit layoutbased on a global analysis of the total chip area reduction; anddetermining an optimal height and length parameter for rows of the firstdesign layout, wherein the means for determining the optimal lengthparameter comprises: proposing a possible row length values for each rowof the first design layout such that a total clip area is reduced; andstoring said possible row length values as a first set in memory. 61.The computer program product of claim 60, further comprising:calculating a minimum height of each row corresponding to each possiblerow length value stored in the set; generating a second set of possiblerow height values wherein each possible row height is greater than thecalculated minimum height; storing the second set in memory; iterativelycalculating total chip area values using each possible row length valuestored in the first set and each possible row height value stored in thesecond set; and determining the optimal total chip area from theiteratively calculated total chip area values.